> can any 1 help me in writing a code for 6 to 16 bit programmable > parallel to serial converter. What do you have already done? Show your work and then ask your questions. > for 6 to 16 bit programmable parallel to serial converter. Is that a simple loadable shift register? Draw a picture or just add more information. For Serial in – parallel out shift registers, all data bits appear on the parallel outputs following the data bits enters sequentially through each flipflop. The following circuit is a four-bit Serial in – parallel out shift register constructed by D flip-flops. VHDL Code for Serial In Parallel Out Shift Register. I'm creating an n bit shift register. When the enable signal is high, I want the shift register to shift n times, irrespective of whether enable continues to be high or low. How to install hp laserjet 1000 on windows 7 and vista 32 bit windows 7. I've put a for loop to shift n times inside a process. My code is given below. I don't think the for loop is working, as the shifting is not restricted to n times. Where am I going wrong? Library ieee; use ieee.std_logic_1164.all; entity SReg is generic ( n: integer:= 4 ); port( clk: in std_logic; reset: in std_logic; enable: in std_logic; --enables shifting parallel_in: in std_logic_vector(n-1 downto 0); s_in: in std_logic; --serial input s_out: out std_logic --serial output ); end SReg; architecture behavioral of SReg is signal temp_reg: std_logic_vector(n-1 downto 0):= (Others => '0'); begin process (clk,reset) begin if (reset = '1') then temp_reg. In VHDL, a for loop executes in zero time. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. This is what's happening in your code. The entire loop is executing in a single clock cycle, and the value of s_out is only going to change once - to the value it was when the loop ended, which in this case is s_in shifted by 4. What you really want is a loop where each iteration occurs on a new clock edge. This allows for s_in to be shifted out of s_out ever clock cycle. Performing a loop where each iteration occurs on a clock edge does not require a for loop command, instead it takes advantage of the sensitivity list of the process. Here's how: A process is triggered every time one of the signals on the sensitivity list ('clk, reset' in this case) changes. This means that the process is already looping every clock cycle (if a clock is in the sensitivity list). You can use this to your advantage in order to perform a for-loop type operation, where every iteration of the loop occurs on a clock cycle. First you need a counter: process(clk,reset) variable shift_counter: integer:= 0; begin shift_counter keeps track of how many iterations (or shifts) have occurred so far. You'll compare shift_counter to n-1 to see if you're done yet. Next it might be a good idea to think of the states your process will be in. Perhaps a wait state for when the process is not shifting, and a shifting state for when it is. The state signal definition: TYPE POSSIBLE_STATES IS (waiting, shifting); signal state: POSSIBLE_STATES; In the process proper: case state is when waiting => Ok, so what happens when we're waiting for an enable? It would be a good idea to set all (driven) variables to a known value. This means that maybe something like this is a good idea: shift_counter:= 0; temp_reg shift_counter:= shift_counter + 1; s_out = n-1) then state '0'); TYPE POSSIBLE_STATES IS (waiting, shifting); signal state: POSSIBLE_STATES; begin process(clk,reset) variable shift_counter: integer:= 0; begin if(reset = '1') then temp_reg '0'); state shift_counter:= 0; temp_reg shift_counter:= shift_counter + 1; s_out = n-1) then state. @stanri's answer is impresively thorough and quite accurate. If I may summarize/clarify the first statement though, the 'for' statement in an HDL simply expresses 'syntactic replication' not 'sequential execution'. That is to say, it simply generates more hardware elements (gates), and does not inform process flow. ![]() I would say the loop is expanded at elaboration time (compilation), not that it 'executes in zero time', after all at runtime there will still be propagation delay through the elements generated by the 'for' construct. Don't start by writing VHDL code, start by drawing logic schematics (at least at some level of abstraction). At the end of the day HDL is just a text-based way of expressing the content of logic schematics.
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